Analog to digital converters are utilized in a wide variety of applications. Converters of this type employed in frequency division multiplexing applications require that particular attention be given to the signal-to-noise (S/N) ratio. Since the quantization error inherent in analog to digital converters is a source of noise, the S/N ratio is dependent upon the number of bits developed by the analog to digital converter. A digital output of thirteen to fifteen bits is usually required to obtain an acceptable S/N ratio in most telecommunications applications. Although it is possible to construct a standard fifteen bit analog to digital converter utilizing present technology, such a converter is costly to implement due to the very tight constraints which must be placed upon the operation characteristics of the components utilized within the analog to digital converter in order to achieve the necessary linearity an in order to minimize the amount of drift versus time and the amount of drift versus temperature experienced by such an analog to digital converter. Generally the analog to digital converter must be of the successive approximation type due to the high speed conversion requirements. An all parallel (FLASH) analog to digital converter meets the high speed requirement but is generally not used due to its very high complexity and cost.
A two-step conversion approach such as is employed in an analog converter identified by model number ADC16/4 manufactured by the assignee of the present application, utilizes a technique which reduces the constraint of initial accuracy of the components through the use of a programmable read-only memory (PROM) which contains a binary digital word representative of the deviation of the analog to digital converter from the true conversion, which binary digital error word is subtracted from (or added to) the result of the conversion operation to compensate for the deviation of converter output from the true output due to variations in characteristics of the components comprising the A/D converter. Although such a correction method does reduce the constraint of the initial accuracy of said components, this two-step technique does not affect time-temperature requirements and, in addition, is a costly approach to obtain the desired objective.
Since the nature of the signal to be converted in telecommunication applications is noise-like, the average signal is considerably smaller than the full-scale input range of the analog to digital converter. This statement implies that the resolution requirements can be relaxed for large signals, with little deterioration in signal to noise ratio, since the probability of occurrence of large signals is small. As an example, no error is created by an analog to digital converter having a large error for large signals if large signals never occur. Thus, an objective of the present invention to avoid the disadvantages of prior art analog to digital converters by providing an analog to digital converter whose resolution is a function of the magnitude of the analog signal to be converted.